The present invention relates to an integrated memory and a method for operating an integrated memory.
With increasing storage density and increasing miniaturization of integrated memories, in particular, in the form of DRAMs (Dynamic Random Access Memories), it is generally becoming more and more difficult to fabricate memory modules. This is principally due to the fact that an increasingly greater effort and expense are required to realize increasingly larger numbers of defect-free memory cells. For this reason, present-day DRAM memory modules usually have a large number of redundant memory cells that can replace defective normal memory cells. This means that numerous inactive redundant memory cells are provided in order to replace, if appropriate, defective normal memory cells by the redundant memory cells. The redundant memory cells are usually activated by programming programmable elements, for example, in the form of so-called laser fuses or electrically programmable fuses, which can be used to program an address of one or more normal memory cells that will be replaced.
With increasing circuit miniaturization, specific semiconductor effects come more and more into play. One of these artifacts is e.g. a variable memory cell time or retention time, also called VRT (Variable Retention Time). In memory cells affected by VRT, the memory time or retention time of the cell changes suddenly. Usually, a memory cell can store, for a specific time, for example 200 ms, enough charge to achieve a sufficiently strong read signal during the read-out of the memory cell. This memory behavior usually does not change significantly over the operating time of the memory module. In memory cells affected by VRT, however, the memory behavior changes suddenly and completely unpredictably. Thus, it can happen e.g. that a memory cell affected by VRT, after days in operation, suddenly changes its memory behavior in such a way that it can store its charge e.g. only for a time of 10 ms, instead of for a time of 200 ms. This state can change again after a period of time, so that the affected memory cell again has the normal memory behavior or the normal retention time of 200 ms.
The problem of a variable memory cell time represents a serious abnormal behavior since affected memory cells, in the application, can lead to a failure and thus to an abnormal behavior of the entire memory. What is more, it is practically impossible to detect and find memory cells affected by VRT in a functional test and to repair them by redundant memory cells, since they mainly exhibit normal behavior during the test phase, which is generally carried out directly after the fabrication of the memory. If a memory product is affected by VRT, then it cannot be supplied to the customer, but rather must be considered to be a reject. To date, it has been attempted to reduce the problem of variable memory cell time to the largest possible extent by technological measures, for example, by avoiding any type of dislocations in the silicon.
It is accordingly an object of the invention to provide an integrated memory and a method of operating the integrated memory which overcomes the above-mentioned disadvantages of the prior art apparatus and methods of this general type.
In particular, it is an object of the invention to provide an integrated memory that can, for the most part, be operated reliably against the background of the abovementioned problem area. Furthermore, it is an object of the present invention to specify a method that allows the integrated memory, for the most part, to be operated reliably against the background of the abovementioned problem area.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory including: a memory cell array having a plurality of memory cells; a read/write amplifier for evaluating and amplifying data signals being read out from or written to the plurality of memory cells of the memory cell array; and an error correction circuit connected to the read/write amplifier. The error correction circuit is capable of being activated when reading out from or writing to the memory cell array. The error correction circuit is for receiving and checking the data signals, which are being read out from or written to the memory cell array, for errors. The error correction circuit, upon detecting an erroneous data signal, corrects the erroneous data signal by inverting the erroneous data signal and outputting a corrected data signal.
The error correction circuit checks the data signals, which are received by it during the read-out or writing, for errors, and in the case of a detected erroneous data signal, corrects the erroneous data signal by inverting it and outputs this corrected data signal. Consequently, the invention provides a memory architecture and an operating method which lead to an efficient realization of an error-tolerant memory. As a result of this, in particular the abovementioned artifacts, such as, VRT can be corrected without being manifested externally to the user of the memory.
In this case, the invention has the advantage that an implementation of an error correction circuit requires practically no additional area outlay and causes virtually no impairment of the memory access times. Since, in principle, any form of single-bit errors can be corrected by the error correction circuit, the redundancy provided in the form of redundant memory cells can be correspondingly reduced. An additional area outlay that is initially necessary in connection with the error correction circuit can thus be practically compensated for.
In one embodiment of the invention, a logic circuit is provided in the error correction circuit. This logic circuit checks the received data signals for errors in accordance with an error correction method according to Hamming, and in the case of a detected erroneous data signal, corrects the erroneous data signal by inverting it. The application of the Hamming method is associated with the observation that usually only a single memory cell of the entire memory is affected by VRT in a semiconductor memory. The implementation of the Hamming method enables an efficient and comparatively simple realization of an error-tolerant memory.
In a further advantageous embodiment of the memory, the memory is designed in a so-called prefetch architecture. In a prefetch architecture, data of a first bit width from different areas of the memory cell array are fed in parallel from the memory cell array to the read/write amplifier and output successively in units of a second bit width. In this case, the error correction circuit is advantageously used for checking and correcting the units of data of the second bit width. The additional area outlay can be kept particularly small in the case of a memory in prefetch architecture.
In particular, the memory cell array is subdivided into a plurality of memory cell blocks, which are connected to the read/write amplifier for the parallel read-out or writing of the data. The error correction circuit is advantageously connected between the read/write amplifier, embodied as a second read/write amplifier (secondary sense amplifier), and an output circuit for outputting the data, which is embodied as a multiplexer circuit. In general, it has been recognized as advantageous that, in the case of a greater degree of xe2x80x9cprefetchingxe2x80x9d (for example in the case of a transition from eight-fold prefetch to 16-fold prefetch), the additional area outlay in connection with the error correction circuit furthermore decreases significantly.
It has been recognized as the basis of a further advantageous embodiment of the invention that the so-called refresh mode of a dynamic memory module can be used as a functional test for detecting memory cells affected by VRT. In a refresh mode of a dynamic memory, stored data signals of selected memory cells are refreshed. In accordance with one embodiment of the invention, the error correction circuit and the read/write amplifier can be activated in the refresh mode of the memory. In this mode, the error correction circuit checks the data signals being refreshed, which are received by it, for errors, and in the case of a detected erroneous data signal, corrects the erroneous data signal by inverting it. The corrected data signal is subsequently written back to the relevant memory cell. This enables an efficient module test for detecting VRT during the operation of the memory.
In a further advantageous embodiment of the invention, a memory circuit is connected to the error correction circuit. This memory circuit can store an address of a memory cell in which an erroneous data signal is stored. Furthermore, it is advantageous to provide a repair circuit connected to the error correction circuit and having electrically programmable elements, for example, in the form of electrical fuses. This serves for driving the error correction circuit in such a way that checking and correction by the error correction circuit are effected only in the case when a data word has an erroneous data signal or bit stored in a memory cell and the erroneous data signal is detected. This enables an efficient repair of the memory during operation. This is based on the insight that, according to experience, an error on account of VRT usually occurs only in an individual memory cell of the memory.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for operating an integrated memory. The method includes steps of: providing a memory cell array including a plurality of memory cells; providing a read/write amplifier for evaluating and amplifying data signals being written to or read out from the plurality of memory cells; connecting an error correction circuit to the read/write amplifier; providing the error correction circuit with data signals of selected memory cells that are being written to or read out from; and in the error correction circuit, checking the data signals for errors, and when detecting an erroneous data signal, correcting the erroneous data signal by inverting the erroneous data signal and outputting a corrected data signal.
In accordance with an added feature of the invention, the step of checking the data signals for errors is performed using a Hamming error correction method.
In accordance with an additional feature of the invention, the step of checking the data signals for errors is performed in a refresh mode in which stored data signals of selected memory cells will be refreshed; and during the step of checking the data signals for errors, the error correction circuit checks the data signals that will be refreshed for errors, and when an erroneous data signal is detected, the error correction circuit provides the corrected data signal by inverting the erroneous data signal, and the corrected data signal is subsequently written back to a relevant memory cell.
In accordance with another feature of the invention, the method includes: performing the step of checking the data signals for errors using a Hamming error correction method implemented by the error correction circuit; for each data word of a plurality of data words, checking a parity for a plurality of data bit groups of different selected bits of the data word; and including data signals from different word lines of the memory cell array when performing the step of checking the parity.
In accordance with a further feature of the invention, the method includes: performing the step of checking the data signals for errors using a Hamming error correction method implemented by the error correction circuit; for each data word of a plurality of data words, obtaining a plurality of parity results by checking a parity for a plurality of data bit groups of different selected bits of the data word; and storing the plurality of the parity results of each data word of the plurality of the data words in memory cells present on a plurality of word lines.
In accordance with a further added feature of the invention, the method includes: performing the step of checking the data signals for errors using a Hamming error correction method implemented by the error correction circuit; for each data word of a plurality of data words, obtaining a plurality of parity results by checking a parity for a plurality of data bit groups of different selected bits of the data word; and storing the plurality of the parity results of each data word of the plurality of the data words in memory cells present on at least one word line exclusively provided therefore.
In accordance with another added feature of the invention, the method includes: performing the step of checking the data signals for errors using a Hamming error correction method implemented by the error correction circuit; for each data word of a plurality of data words, obtaining a plurality of parity results by checking a parity for a plurality of data bit groups of different selected bits of the data word; and storing the plurality of the parity results of each data word of the plurality of the data words in memory cells present on at least one bit line exclusively provided therefore.
In accordance with another additional feature of the invention, the method includes: performing the step of checking the data signals for errors using a Hamming error correction method implemented by the error correction circuit; for each data word of a plurality of data words, obtaining a plurality of parity results by checking a parity for a plurality of data bit groups of different selected bits of the data word; and storing-sequential ones of the plurality of the parity results of each data word of the plurality of the data words in memory locations within an already activated word line or word line set.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated memory and method for operating an integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.